There have been proposed various structures for a printed wiring board having a build-up portion that is electrically connecting a plurality of wire patterns laminated via insulating layers to each other through via holes. For example, with respect to this type of printed wiring board, when a semiconductor device mounted thereon is turned on and off at high speed, switching noise occurs and thus the potential of a power supply line is instantaneously reduced in some cases. In order to suppress such instantaneous reduction of the potential, it has been proposed that a capacitor portion is connected between the power supply line and the ground line for decoupling.
For example, Japanese Published Unexamined Patent Application No. 2004-87971 has proposed that a thin film capacitor portion is contained in a printed wiring board (see FIG. 21). In this publication, a laminate body 106 containing an exfoliation layer 101, an electrode layer 102, a dielectric layer 103, an electrode layer 104 and an insulating layer 105 which are laminated on a silicon wafer 100 in this order is prepared (see FIG. 21(a)), and two filled vias 107 and 108 are formed in the insulating layer 105. Subsequently, a substrate 110 having a ground electrode 111 and a power supply electrode 112 is separately prepared, and the laminate body 106 is turned over and adhesively attached to the substrate 110 so that the filled vias 107 and 108 face the electrodes 111 and 112, respectively (see FIG. 21(b)). Thereafter, the capacitor portion 113 (the portion including the three layers of the electrode layer 102, the dielectric layer 103 and the electrode layer 104) is patterned into a predetermined shape (see FIG. 21(c)), and a polyimide layer 114 coating the capacitor portion 113 is formed. A hole is formed so as to extend from the upper surface of the polyimide layer 114 to the electrode layer 102, and then the hole is filled with electrically conductive paste to form a filled via 115. Furthermore, likewise, a hole is formed so as to extend from the upper surface of the polyimide layer 114 to the filled via 108, and then the hole is filled with electrically conductive paste to form a filled via 116 (see FIG. 21(d)). The filled vias 115 and 116 are connected to each other by an outer layer pattern 117, whereby charges are supplied from the power supply electrode 112 to the electrode layer 102 of the capacitor portion 113.